The present invention relates in general to semiconductor integrated circuit (IC) device manufacturing technologies; and, more particularly, the invention relates to a technique which is applicable for use in the manufacture of semiconductor IC chips with redundancy circuitry for correcting or xe2x80x9ccuringxe2x80x9d defective bits through the use of fuse cutting processes.
Currently available semiconductor large-scale integrated circuit (LSI) memory devices, including, but not limited to, dynamic random access memory (DRAM) chips,are typically designed to offer redundant functions for correcting or curing bit defects that can take place in the manufacture thereof,thus increasing production yields.
One prior known approach to achieving such defect curing function is to pre-equip memory circuitry with redundant or xe2x80x9csparexe2x80x9d rows and columns (redundancy circuit), one or several of which is/are selected for alternative use upon inputting of an address signal to a defective cell (malfunction bit) within a memory array to ensure that a memory chip will no longer exhibit operation failures as a whole even when the circuit partly contains defective portions therein.
Replacing or xe2x80x9cswitchingxe2x80x9d between a defective portion and its corresponding spare part is performed by cutting a fuse connected to an address switch/change circuit operatively associated therewith. Although electrical disconnection or cut-off of such fuse may be accomplished by presently available current blowout schemes or laser fusion methods in most cases, the latter is preferably employable for such purposes because of several which are advantages afforded thereby, including enhanced flexibility of replacement software programs along with an increased area efficiency. A prior art LSI memory device with built-in laser meltable fuse elements for use in replacing defective cells with redundant cells has been disclosed in patent publications such as, for example, Japanese Patent Laid-Open No. 25055/1990.
Built-in defect-curing fuse elements of the type referred to above are typically made of electrode lead materials, such as metals or polycrystalline silicon or other similar suitable conductive easy-to-melt materials, and are manufacturable on the principal surface of a silicon wafer simultaneously with the fabrication of semiconductor elements and/or associative electrical on-chip leads (at the wafer processing stage). In cases where a defective memory cell is found through probe test/inspection at the final stage of such wafer processes, a selected one of the fuse elements is blown out or cut away by irradiation using a laser beam, thereby allowing an address inherently corresponding to the defective cell to be allocated to a redundant cell.
The present inventor has studied the manufacturing processes of an LSI memory with redundant circuitry for use in curing defective bits by use of fuse cutoff techniques. A result of such study will be set forth below. Note that this should not be deemed as prior art, but is uniquely evaluated art, as will be summarized as follows.
As previously stated, memory cell defect curing is achieved by cutting or xe2x80x9cbreakingxe2x80x9d for disconnection a selected fuse element in the address change/switch circuit at the final stage in the wafer processing procedure. In the case of employing such a laser blowout scheme, the cutting of a fuse is carried out by irradiating it with a laser beam from a light source placed over a wafer of interest. To this end, it a certain region of the principal surface of the wafer having more than one fuse formed therein should be formed such that part of an insulative film overlying the fuse is removed to form an opening to thereby permit the energy of such laser beam to readily reach the fuse.
Most wafers are formed such that a surface protection film, known as a xe2x80x9cfinal passivation filmxe2x80x9d in the semiconductor art, is formed to overlie a metal lead pattern of the uppermost layer, which film in turn is covered by a heat-resistant resin layer made of polyimide that is deposited thereon. The passivation film is a protective film for use in preventing an unwanted mixture or xe2x80x9cinvasionxe2x80x9d of a water component from wafer surfaces into on-chip electrical circuitry, which may typically be comprised of a dense dielectric film,such as a silicon oxide film or silicon nitride film fabricated by plasma chemical vapor deposition (CVD) techniques. Regarding the resin layer, this is formed by deposition for various intended purposes,including elimination of the so-called xe2x80x9csoft errorsxe2x80x9d otherwise occurring due to alpha (xcex1) ray irradiation, elimination of chip surface damage due to residual silicon fillers in chip sealing resin (mold resin), and moderation or xe2x80x9crelaxationxe2x80x9d of stresses at the interface between the passivation film and the mold resin.
As the passivation film and resin layer referred to above are formed to relatively increased thicknesses in the order of micrometers (xcexcm), those portions of the passivation film and resin layer which overlie the fuse must be removed prior to execution of probe test/inspection tasks. Alternatively, in case the fuse is formed of a conductive layer at a relatively lower layer, an interlayer dielectric film underlying the passivation film will also have to be removed away.
Removal of specified components of the passivation film and resin layer overlying the fuse may be attained by forming on or over the resin layer a first photoresist film provided with an opening or hole overlying the fuse, and by then letting the resin layer overlying the fuse undergo wet etching treatment with the photoresist film being used as a mask therefor. This photoresist film is also provided with an opening at a location that overlies a pad constituting an external connection terminal of the chipxe2x80x94the pad is made of part of the uppermost lead and thus is also called a xe2x80x9cbonding padxe2x80x9dxe2x80x94thus allowing the resin layer overlying the pad to be subject to etching simultaneously.
Then, after having removed the first photoresist film, a second photoresist film having an opening overlying the fuse, is fabricated on the resist layer, which is used as a mask to apply dry etching to the passivation film overlying the fuse (and also its underlying interlayer dielectric film as the need arises), thereby forming a fuse-cut opening that overlies the fuse. This photoresist film is also provided with another opening overlying the pad to allow simultaneous etching of the passivation film overlying the pad, to thereby cause the pad to be exposed on the surface thereof.
Unfortunately the fuse/pad-hole fabrication processes referred to above have a problem concerning an increase in the number of wafer process steps, because of a need for two separate photolithography steps, one of which is for fabrication of the first photoresist film used in removing the resin layer, and the other of which is for formation of the second photoresist film used to remove the passivation film (and its underlying interlayer dielectric film where necessary). In this case the process technology is modifiable to continuously use, after completion of the wet etching of the resin layer using the first photoresist film, this first photoresist film for effecting a dry etching of the passivation film; however such approachxe2x80x94namely, using the same photoresist film for removal of the resin layer by dry etching and also for removal of the passivation film (and its underlying interlayer dielectric film if needed)xe2x80x94is not preferable because of the risks of a decrease in etching controllability.
One way of preventing such increase in the number of wafer process steps while retaining the etching controllability required is to let the above-noted resin layer be made of photosensitive resin materials. A fuse/pad-hole fabrication procedure in the case of employing a photosensitive resin involves first depositing a resin layer made, for example, of a photosensitive polyimide resin layer, on or over the passivation film; and then, openings or holes that overlie a fuse and a pad of interest are defined through exposure and development processes applied to this resin layer. Next, the resin layer is used as a mask to remove, by dry etching techniques, specified portions of the passivation film overlying the fuse and pad to thereby form a fuse-cutting opening that overlies the fuse, while simultaneously forcing the pad to be exposed at its surface.
In this way, replacing the ordinary non-photosensitive resin with a photosensitive resin for deposition on or over the passivation film makes it possible to achieve the intended fuse/pad-opening fabrication processes while reducing or minimizing the number of wafer process steps involved.
The advantage of the fuse/pad-hole forming processes employing the photosensitive resin as stated above does not come without an accompanying problem, which is as follows.
Those wafers containing therein defective bits which are cured by fuse blowout/cutoff processing are cut into chips, which are then transported toward the succeeding facility for post-processing (chip packaging/assembly processes). Subdividing a wafer into chips is done by using a dicing blade instrument to cut a lattice-shaped scribe region that is provided between adjacent ones of a plurality of chip regions partitioned on the wafer""s principal surface. In this case, cutting thick resin layers deposited on the wafer surface can result in a decrease in the lifetime of the dicing blade due to the fact that most or all dicing blade tools are inherently designed for use in cutting silicon wafers made of brittle materials. Such blade lifetime reduction might necessitate increases in the frequency of parts replacement, which in turn serves to increase LSI production costs undesirably.
A remedy for the foregoing problem is to make use of a specially designed photomask for use in defining, in the photosensitive resin layer those openings or apertures overlying fuses and pads by exposure and development processing, which photomask is patterned to ensure that any residual components of such photosensitive resin layer will hardly occur at locations overlying scribe regions. However, this remedy suffers from a further penalty: a test element group (TEG) that is covered by no mask portions will possibly be destroyed during dry etching of the passivation film overlying the fuses and pads (along with or without its underlying interlayer dielectric film) with the scribe region-exposed photosensitive resin layer being used as a mask, the TEG having test elements and pads for probe-test use formed therein and being laid out in scribe regions of wafers.
Another problem created by the above approach is that execution of TEG testing with the passivation film removed and with a lead layer of metal, such as aluminum,exposed would result in the metal lead layer causing migration leading to electrical disconnection or an open-circuit.
In view of the above, in the manufacturing processes of memory LSIs with built-in redundant circuitry for curing bit defects by fuse cutoff techniques, it is essential to avoid the above-stated problems to reduce manufacturing costs.
It is therefore an object of the present invention to provide a new and improved technique which is adaptable for use with semiconductor integrated circuit devices of the type which include built-in redundant circuitry for curing defective bits by fuse cutoff procedures, which technique is capable of suppressing reduction in the life of a dicing blade instrument used during cutting of a wafer into chips, while simultaneously eliminating destruction of TEGs formed in scribe regions of the wafer.
It is another object of the instant invention to facilitate the manufacture of semiconductor integrated circuit devices having built-in fuse elements,while at the same time increasing production yields.
It is a further object of the invention to preclude or minimize destruction of test-use elements.
These and other objects, features and advantages of the invention will become apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
Some representative ones of the inventive contributions as disclosed and claimed herein will be briefly explained below.
In accordance with one aspect of the invention, a semiconductor integrated circuit device with built-in fuse elements is arranged so that laminated electrical lead layers include a layer as high in level as possible for use in constituting requisite fuse elements to thereby allow openings provided in an insulative film overlying such fuse elements to have a decreased depth, which in turn makes it possible to facilitate the manufacture of the semiconductor integrated circuit device,while increasing the production yields thereof.
In accordance with another aspect of this invention, use of a photosensitive resin film coating the surface of a test-use element or elements as formed in scribe regions enables elimination of test-use element destruction even in the case of employing such a photosensitive resin film.
In accordance with a further aspect of the invention, letting fuse elements be made of a certain lead layer that is the same as a second electrode of a capacitive element allows a photosensitive resin film to be formed so as to merely cover a conductive layer or layers overlying the fuse elements, which in turn makes it possible to reduce the requisite area of such photosensitive resin film in scribe regions, thus increasing or extending the lifetime of a dicing blade.